Clocked pass transistor and complementary pass transistor logic circuits

ABSTRACT

A logic circuit and associated method are provided to improve the switching performance of integrated circuit devices. The logic circuit includes a pass transistor logic circuit, a CMOS transistor pair connected as an inverter and having an input coupled to the output of the pass transistor logic circuit, a clocking transistor coupled between the inverter and a potential terminal to selectively enable the inverter according to a first clocking signal, and a precharge transistor coupled between the inverter output and a potential terminal to precharge the inverter output low according to a second clocking signal.

FIELD OF THE INVENTION

[0001] The present invention relates to improving the switching performance of an integrated circuit, and more particularly to a logic circuit employing clocked pass transistor and complementary pass transistor logic.

BACKGROUND OF THE INVENTION

[0002] Pass transistor logic is one of the oldest logic techniques used in forming integrated circuits. Prior to the advent of complementary metal-oxide semiconductor (CMOS) technology currently popular in integrated circuit fabrication, pass transistor logic had been used in n-channel metal-oxide semiconductor (NMOS) circuits. Pass transistor logic was subsequently implemented in CMOS technology circuits. For example, CMOS pass transistor logic has been applied in microprocessors and other circuits. Comparisons have been made between pass transistor logic and standard CMOS logic for a variety of different applications and power supply voltages.

[0003] Static pass transistor logic circuits of the type shown in FIGS. 1-2 have been used in CMOS technology and integrated circuits, for example, in the design of microprocessors and other structures. However, static pass transistor logic circuits suffer from a common problem: there is a threshold voltage drop at the input across a pass transistor. As illustrated in FIG. 1, if the input voltage source 28 is VDD at a logical “1” or high logic state, then the voltage at a node 34 (the input to the inverter 22) will rise only to VDD-VTN, where VTN is the threshold voltage of the transistor 26. In addition, the rise time required for the node 34 to reach this voltage (VDD-VTN) is theoretically infinite, since the NMOS pass transistor 26 has a final state which theoretically has infinite resistance.

[0004] This problem is exacerbated if, as shown in FIG. 2, the output of one pass transistor 32 is used to drive the gate of another transistor 26. In the circuit shown in FIG. 2, the voltage at node 34 (the input to the inverter 22) will charge only to VDD-2VTN. This result is unacceptable in low power supply circuits and therefore design rules preclude such a configuration.

[0005] Various techniques have been used to overcome these problems. One technique is the use of level restore circuits, examples of which are illustrated in FIGS. 3-4. Referring to FIG. 3, a level restore circuit 30 is illustrated, including a pass transistor 26 and level restore transistor 38, in which the output of the inverter 22 is fed back to control a PMOS level restore transistor 38. If the input to the inverter 22 at the node 34 is switching high, then the output of the inverter 22 is switching low, thus driving the gate of the PMOS level restore transistor 38 to pull up the input to the inverter 22 at the node 34. This is a positive feedback circuit which tends to latch the input high regardless of how slowly the original input signal was rising. In this manner, the level restore circuit 30 overcomes the threshold voltage drop at the input to the inverter 22. The level restore circuit 40 shown in FIG. 4 is essentially equivalent to the level restore circuit 30 of FIG. 3, except that an additional inverter 44 is used to drive the gate of the PMOS level restore transistor 42 to pull up the input to the inverter 22 at the node 34.

[0006] Another problem plaguing pass transistor logic circuits is signal propagation delay. For a plurality of pass transistor stages connected in series, each stage including a pass transistor circuit and an inverter, when the logic state of the first pass transistor circuit changes state, a chain reaction ensues in which every output changes state in sequence. For example, FIG. 9 illustrates a plurality of pass transistor circuits 26 and inverters 22 connected in series. The noted chain reaction causes a long signal delay through the chain, wasting energy and causing high power dissipation. Concerns about propagation delay of pass transistor logic spurred the development of prediction logic circuits attached to each inverter in the chain. However, incorrect predictions may lead to the combination of an input and an output of an inverter at a same logic state, which is not a stationary or stable condition for such a circuit.

[0007] Accordingly, there is a strong desire and need to improve the switching performance of integrated circuits using logic that overcomes the voltage drop and propagation delay problems of pass transistor logic.

SUMMARY OF THE INVENTION

[0008] A logic circuit and associated method are provided to improve the switching performance of integrated circuit devices. Clocked pass transistor logic is combined with precharge circuitry, and the output nodes of clocked inverters receiving the output of the pass transistor circuits are precharged low. The precharging reduces signal propagation delays and can significantly increase the performance of switching in integrated circuits employing pass transistors.

[0009] The logic circuit includes a pass transistor logic circuit; a clocked inverter circuit including a CMOS transistor pair having a gate of a first transistor coupled to a gate of a second transistor, the coupled gates being coupled to an output of the pass transistor logic circuit, and a first source/drain region of the first transistor coupled to a first source/drain region of the second transistor, the coupled first source/drain regions being coupled to an output of the clocked inverter circuit, wherein a second source/drain region of the first transistor is coupled to a first potential terminal. The logic circuit further includes a clocking transistor coupled between the second transistor and a second potential terminal and having a gate coupled to a first clocking signal and a precharge transistor coupled between the clocked inverter output and the second potential terminal and having a gate coupled to a second clocking signal.

[0010] In another aspect of the invention, switching performance is improved by allowing only low to high transitions at the output of the clocked inverter circuit. The output of the clocked inverter circuit is precharged low. If the output of the pass transistor logic connected to the input of the clocked inverter is attempting to switch high and thus the output of the inverter is attempting to switch low, then the output of the clocked inverter will simply remain low at the precharged state. If the output of the pass transistor logic is attempting to switch low and thus the output of the inverter is attempting to switch high, then the output of the clocked inverter will transition from the low precharge to a high state quickly through low resistance PMOS transistors in the clocked inverter circuit.

[0011] In another aspect of the invention, a clocking transistor and a precharge transistor are used to assist in precharging the output of the inverter circuit while avoiding unstable circuit conditions. The clocked inverter circuit includes one or more clocking transistors which couple the inverter circuit to ground only during periods in which the inverter output is not being precharged. The gate of the clocking transistor is controlled by a first clocking signal, and the gate of the precharge transistor is controlled by a second clocking signal, each of the first and second clocking signals having a first state (e.g., low) during a precharge phase and then transitioning to a second state (e.g., high) during an inverter operation phase. The first and second clocking signals are complementary signals so that during the precharge phase, the precharge transistor is gated (e.g., high state) while the clocking transistor is not gated (e.g., low state), and therefore the output of the inverter circuit is precharged low and the inverter is not enabled. During a subsequent operation phase, precharging ceases, the inverter is enabled and the output of the pass transistor circuit controls the output of the inverter circuit. The output of the inverter circuit is evaluated during the operation phase.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The foregoing and other features and advantages of the invention will become more apparent from the detailed description of the exemplary embodiments of the invention given below with reference to the accompanying drawings in which:

[0013]FIG. 1 illustrates a known static pass transistor logic circuit;

[0014]FIG. 2 illustrates another known static pass transistor logic circuit;

[0015]FIG. 3 illustrates a known pass transistor logic circuit having level restore circuitry;

[0016]FIG. 4 illustrates another known pass transistor logic circuit having level restore circuitry;

[0017]FIG. 5 illustrates a logic circuit in accordance with an exemplary embodiment of the invention;

[0018]FIG. 6 illustrates a timing diagram for clocking signals in accordance with the exemplary embodiment shown in FIG. 5;

[0019]FIG. 7 illustrates a simple pass transistor logic circuit that may be used in accordance with an exemplary embodiment of the invention;

[0020]FIG. 8 illustrates a complementary pass transistor logic circuit that may be used in accordance with another exemplary embodiment of the invention;

[0021]FIG. 9 illustrates a plurality of conventional logic circuits connected in a chain;

[0022]FIG. 10 illustrates a plurality of logic circuits connected in a chain in accordance with another exemplary embodiment of the invention; and

[0023]FIG. 11 illustrates a processor system formed in accordance with another exemplary embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

[0024] The invention provides a logic circuit and associated method which may be used in forming integrated circuit devices. While the invention is described below with reference to a memory system, including memory devices as representative integrated circuit devices which may include the logic circuit of the present invention, it should be understood that the invention may be used with any type of system which uses logic circuits.

[0025] In addition, while the invention is described below with reference to simple control logic circuits, including simple pass transistor circuits which may used with the logic circuit of the present invention, it should be understood that simple pass transistor circuits are not required and the invention may be used with any type of control logic circuitry, for example complementary pass transistor circuitry.

[0026] Referring to FIG. 5, an exemplary logic circuit 100 in accordance with the present invention is illustrated. The logic circuit 100 illustrated in FIG. 5 includes two stages 112 a and 112 b, each stage (e.g., 112 a) including a precharge circuit which includes a precharge transistor 110 a, a clocked inverter circuit 109 a, and a control logic circuit formed as a pass transistor circuit 102 a. Each of the pass transistor circuits 102 a, 102 b may, for example, be a simple pass transistor circuit 102′ as illustrated in FIG. 7, or a pair 102″ of complementary pass transistor circuits having complementary inputs and outputs as shown in FIG. 8, or other pass transistor circuit arrangement. For the exemplary complementary pass transistor circuit 102″ of FIG. 8, each complementary output may be connected to a separate clocked inverter circuit 109. The pass transistor circuit 102 in FIGS. 5 and 10 is illustrated as a simple pass transistor circuit (e.g., simple pass transistor circuit 102′ in FIG. 7) for simplicity.

[0027] Each clocked inverter circuit, e.g., clocked inverter circuit 109 a, includes a CMOS transistor pair, including PMOS transistor 104 a and NMOS transistor 106 a, with gates coupled together and connected to the output of the pass transistor circuit 102 a. One source/drain region of each transistor 104 a, 106 a is coupled together and connected to the output of the clocked inverter circuit 109 a. The clocked inverter circuit 109 a also includes a clocking transistor 108 a coupled between the transistor 106 a and a second potential terminal (e.g., ground). The gate of the clocking transistor 108 a is controlled by a first clocking signal φ₁.

[0028] The precharge circuit includes a precharge transistor 110 a coupled between a second potential terminal (e.g., ground) and the output of the clocked inverter circuit 109 a. The gate of the precharge transistor 110 a is controlled by a second clocking signal (e.g., {overscore (φ)}₁). The first and second clocking signals may be complementary signals such that when the first clocking signal (e.g., φ₁) is high, the second clocking signal (e.g., {overscore (φ)}₁) is low, for example as illustrated in FIG. 6.

[0029] Referring to FIG. 6, a timing diagram is shown illustrating the clocking signals φ₁, {overscore (φ)}₁, φ₂, {overscore (φ)}₂ that may be applied to the gates of the clocking 108 a, 108 b and precharge 110 a, 110 b transistors of the logic circuit 100 illustrated in FIG. 5. Note that different clocks are used within the same stage (e.g., φ₁ and {overscore (φ)}₁ are used in a first stage 112 a, and φ₂ and {overscore (φ)}₂ are used in a second stage 112 b). Also note that the clocking signals are time-delayed from one stage 112 a until the next stage 112 b (e.g., φ₂ appears after φ₁). At a first time, e.g., t_(PRECHARGE1), the output of the clocked inverter 109 a of the first stage 112 a is precharged low via gating of the first stage's precharge transistor 110 a, while the first stage's clocking transistor 108 a is not gated. At a second time, e.g., t_(EVAL1), the CMOS transistor pair 104 a, 106 a of the first stage 112 a evaluates the input via gating of the clocking transistor 108 a, while the precharge transistor 110 a is not gated. The second stage 112 b may be precharged and evaluated in a similar fashion, except that the second stage signals ( φ₂ and {overscore (φ)}₂) are delayed relative to the first stage signals (φ₁ and {overscore (φ)}₁), as shown in FIG. 6. In this way, each succeeding stage waits until the preceding stage's output is valid before evaluating its logic decision, thereby avoiding unstable circuit conditions.

[0030] In operation, a plurality of stages of the type illustrated in FIG. 5 may be connected in series, as shown in FIG. 10. As noted, each stage includes a control logic circuit (e.g., a pass transistor circuit 102), an inverter circuit (e.g., a clocked inverter including a clocking transistor 108), and a precharge circuit (e.g., a precharge transistor 110).

[0031] In each stage shown in FIG. 10, a clocking transistor 108 and a precharge transistor 110 are used to assist in precharging the output of an inverter circuit while avoiding unstable circuit conditions. Each clocked inverter circuit 109 (FIG. 5) may include one or more clocking transistors (e.g., clocking transistor 108) which avoid unstable circuit conditions by coupling the inverter circuit to ground only during periods in which the inverter output is not being precharged. The gate of each clocking transistor 108 is controlled by a first clocking signal (e.g., φ₁), and the gate of each precharge transistor 110 is controlled by a second clocking signal (e.g., {overscore (φ)}₁). The first and second clocking signals may be complementary signals so that during the precharge phase, the precharge transistor 110 is gated (e.g., high state) while the clocking transistor 108 is not gated (e.g., low state), and therefore the output of the inverter circuit is precharged low and the inverter is not enabled. During a subsequent operation phase, precharging ceases, the inverter is enabled and the output of the pass transistor circuit 102 controls the output of the inverter circuit. The output of the inverter circuit is evaluated during the operation phase.

[0032] The logic circuit 100 improves switching performance by permitting fast low to high transitions at the output of each clocked inverter circuit 109. As noted, the outputs of the clocked inverters 109 are precharged low. If an output of a clocked inverter 109 is attempting to switch low, then the output will simply remain low at the precharged state. If an output of the clocked inverter 109 is attempting to switch high, then it may do so quickly through low resistance PMOS transistors, for example PMOS transistor 104, in the clocked inverter circuit 109. The PMOS transistor 104 may be made large to speed up the switching time from low to high.

[0033]FIG. 11 illustrates an exemplary processor system 200 which may include a logic circuit 100. Referring to FIG. 11, the processor system 200, which may be a computer system, for example, generally comprises a central processing unit (CPU) 202, for example, a microprocessor, that communicates with one or more input/output (I/O) devices 212, 214, 216 over a system bus 222. The computer system 200 also includes random access memory (RAM) 218, a read only memory (ROM) 220 and, in the case of a computer system may include peripheral devices such as a floppy disk drive 204, a hard drive 206, a display 208 and a compact disk (CD) ROM drive 210 which also communicate with the processor 202 over the bus 222. The RAM 218 includes memory devices having at least one logic circuit 100 constructed in accordance with the invention. In addition, one or more of the other elements shown in FIG. 11 may also include at least one logic circuit 100 constructed in accordance with the invention. It should also be noted that FIG. 11 is merely representative of many different types of processor system architectures which may employ the invention.

[0034] The logic circuit 100 has been described that improves switching performance by overcoming the voltage drop and propagation delays problems of the prior art. These and other advantages are achieved by precharging the output of the inverters low and time-delaying the clocking of sequential stages, so that unstable circuit conditions are avoided during a precharge phase, and only fast low to high transitions occur during an operational phase of the logic circuit 100.

[0035] While the invention has been described and illustrated with reference to specific exemplary embodiments, it should be understood that many modifications and substitutions can be made without departing from the spirit and scope of the invention. Accordingly, the invention is not to be considered as limited by the foregoing description but is only limited by the scope of the appended claims. 

What is claimed as new and desired to be protected by Letters Patent of the U.S. is:
 1. A logic circuit, comprising: a first inverter circuit for receiving a first input logic signal and providing a first inverted output logic signal; a first precharge circuit for precharging the output of said first inverter circuit to a first predetermined voltage in response to a first clock signal; a first enable circuit for enabling operation of said first inverter circuit in response to a second clock signal; said first and second clock signals being arranged such that said first precharge circuit is operative during a time when said first inverter circuit is disabled by said first enable circuit and said first inverter circuit is enabled during a period when said first precharge circuit is inoperative.
 2. A logic circuit as in claim 1, wherein said first and second clock signals are complementary clock signals.
 3. A logic circuit as in claim 1, further comprising a first control circuit providing said first input logic signal to said first inverter, said first control circuit comprising at least one signal pass transistor for passing a logic signal to provide said first input logic signal.
 4. A logic circuit as in claim 3, further comprising: a second inverter circuit for receiving a second input logic signal and providing a second inverted output logic signal, said second inverter circuit being coupled to receive said first output logic signal of said first inverter circuit as said second input logic signal; a second precharge circuit for precharging the output of said second inverter circuit to a second predetermined voltage in response to a third clock signal; a second enable circuit for enabling operation of said second inverter circuit in response to a fourth clock signal; said third and fourth clock signals being arranged such that said second precharge circuit is operative during a time when said second inverter circuit is disabled by said second enable circuit and said second inverter circuit is enabled during a period when said second precharge circuit is inoperative, wherein said third and fourth clock signals are delayed relative to said first and second clock signals.
 5. A logic circuit as in claim 4, further comprising a second control circuit providing said second input logic signal to said second inverter, said second control circuit comprising at least one signal pass transistor for passing a logic signal to provide said second input logic signal.
 6. A logic circuit as in claim 1, wherein said first predetermined voltage is a logic low voltage.
 7. A logic circuit as in claim 6, wherein said first predetermined voltage is ground.
 8. A logic circuit as in claim 4, wherein said second predetermined voltage is a logic low voltage.
 9. A logic circuit as in claim 8, wherein said second predetermined voltage is ground.
 10. A logic circuit, comprising: at least one control logic circuit; at least one inverter including a CMOS transistor pair having a gate of a first transistor coupled to a gate of a second transistor, said coupled gates being coupled to an output of said at least one control logic circuit, and a first source/drain region of said first transistor coupled to a first source/drain region of said second transistor, said coupled first source/drain regions being coupled to an output of said inverter, wherein a second source/drain region of said first transistor is coupled to a first potential terminal; at least one precharge transistor coupled to said inverter and configured to precharge said output of said inverter to a first logic state; and at least one clocking transistor coupled to said inverter and configured to selectively enable said output of said inverter.
 11. A logic circuit as in claim 10, wherein said first logic state is a low logic state.
 12. A logic circuit as in claim 10, wherein said at least one clocking transistor has a gate coupled to a first clocking signal and said at least one precharge transistor has a gate coupled to a second clocking signal.
 13. A logic circuit as in claim 12, wherein said first and second clocking signals are complementary signals.
 14. A logic circuit, comprising: at least one control logic circuit; at least one inverter including a CMOS transistor pair having a gate of a first transistor coupled to a gate of a second transistor, said coupled gates being coupled to an output of said at least one control logic circuit, and a first source/drain region of said first transistor coupled to a first source/drain region of said second transistor, said coupled first source/drain regions being coupled to an output of said inverter, wherein a second source/drain region of said first transistor is coupled to a first potential terminal; at least one clocking transistor having a gate coupled to a first clocking signal, a first source/drain region coupled to a second potential terminal, and a second source/drain region coupled to a second source/drain region of said second transistor; and at least one precharge transistor having a gate coupled to a second clocking signal, a first source/drain region coupled to said second potential terminal, and a second source/drain region coupled to said output of said inverter.
 15. A logic circuit as in claim 14, wherein during a first phase said precharge transistor is configured to precharge said output of said inverter to a low logic state, and during a second phase said clocking transistor is configured to activate said inverter such that said inverter output is not required to change states if said activated inverter first outputs said low state.
 16. A logic circuit as in claim 15, wherein during said first phase, said precharge transistor is configured to couple said output of said inverter to said second potential terminal.
 17. A logic circuit as in claim 15, wherein during said second phase, said clocking transistor is configured to couple said second source/drain region of said second transistor to said second potential terminal.
 18. A logic circuit as in claim 14, wherein said first clocking signal is initially in a low state and said second clocking signal is initially in a high state, permitting said precharge transistor to precharge said inverter output to a low state.
 19. A logic circuit as in claim 18, wherein when said first clocking signal transitions from said initial low state to a high state and said second clocking signal transitions from said initial high state to a low state, said inverter output is set according to said output of said control logic circuit.
 20. A logic circuit as in claim 19, wherein when said output of said control logic circuit initially attempts to place said inverter output in a low state, then said inverter output continues said low state of said precharge.
 21. A logic circuit as in claim 19, wherein when said output of said control logic circuit initially attempts to place said inverter output in a high state, then said inverter output transitions from said low state of said precharge to said high state.
 22. A logic circuit as in claim 14, wherein said at least one control logic circuit comprises a pass transistor control circuit.
 23. A logic circuit as in claim 22, wherein said pass transistor control circuit comprises a pass transistor circuit.
 24. A logic circuit as in claim 22, wherein said pass transistor control circuit comprises a pair of complementary pass transistor circuits.
 25. A logic circuit as in claim 14, wherein said second potential terminal is at ground potential.
 26. A logic circuit as in claim 14, wherein said clocking transistor is an NMOS transistor.
 27. A logic circuit as in claim 14, wherein said precharge transistor is an NMOS transistor.
 28. A logic circuit as in claim 14, wherein said first and second clocking signals are complementary signals.
 29. A logic circuit, comprising: at least two clocked logic circuits, including a first clocked logic circuit having an output coupled to an input of a second clocked logic circuit, each of said first and second clocked logic circuits comprising: at least one control logic circuit; at least one inverter including a CMOS transistor pair having a gate of a first transistor coupled to a gate of a second transistor, said coupled gates being coupled to an output of said at least one control logic circuit, and a first source/drain region of said first transistor coupled to a first source/drain region of said second transistor, said coupled first source/drain regions being coupled to an output of said inverter, wherein a second source/drain region of said first transistor is coupled to a first potential terminal; at least one precharge transistor coupled to said inverter and configured to precharge said output of said inverter to a first logic state; and at least one clocking transistor coupled to said inverter and configured to selectively enable said output of said inverter.
 30. A logic circuit as in claim 29, wherein said first logic state is a low logic state.
 31. A logic circuit as in claim 29, wherein said clocking transistor is configured to selectively enable said output of said inverter according to a first clocking signal, and said precharge transistor is configured to precharge said output of said inverter according to a second clocking signal.
 32. A logic circuit as in claim 31, wherein said first and second clocking signals of said second clocked logic circuit are delayed relative to said first and second clocking signals of said first clocked logic circuit.
 33. A logic circuit as in claim 29, wherein said at least two clocked logic circuits includes a plurality of clocked logic circuits connected with an output of a preceding clocked logic circuit connected to an input of a succeeding clocked logic circuit.
 34. A logic circuit as in claim 33, wherein said control logic circuit of each clocked logic circuit is a pass transistor control circuit, and during a first phase said precharge transistor of each clocked logic circuit is configured to precharge said output of said inverter to a low logic state, and during a second phase said clocking transistor of each clocked logic circuit is configured to activate said inverter such that the inverter output of approximately one of every two of said plurality of clocked logic circuits is not required to change states.
 35. A logic circuit as in claim 34, wherein said pass transistor control circuit for at least one of said plurality of clocked logic circuits comprises a pass transistor circuit.
 36. A logic circuit as in claim 34, wherein said pass transistor control circuit for at least one of said plurality of clocked logic circuits comprises a pair of complementary pass transistor circuits.
 37. A logic circuit as in claim 29, wherein said first and second clocking signals are complementary signals.
 38. A logic circuit, comprising: at least two clocked logic circuits, including a first clocked logic circuit having an output coupled to an input of a second clocked logic circuit, each of said first and second clocked logic circuits comprising: at least one control logic circuit; at least one inverter including a CMOS transistor pair having a gate of a first transistor coupled to a gate of a second transistor, said coupled gates being coupled to an output of said at least one control logic circuit, and a first source/drain region of said first transistor coupled to a first source/drain region of said second transistor, said coupled first source/drain regions being coupled to an output of said inverter, wherein a second source/drain region of said first transistor is coupled to a first potential terminal; at least one clocking transistor having a gate coupled to a first clocking signal, a first source/drain region coupled to a second potential terminal, and a second source/drain region coupled to a second source/drain region of said second transistor; and at least one precharge transistor having a gate coupled to a second clocking signal, a first source/drain region coupled to said second potential terminal, and a second source/drain region coupled to said output of said inverter.
 39. A logic circuit as in claim 38, wherein said first and second clocking signals of said second clocked logic circuit are delayed relative to said first and second clocking signals of said first clocked logic circuit.
 40. A logic circuit as in claim 38, wherein said at least two clocked logic circuits includes a plurality of clocked logic circuits connected with an output of a preceding clocked logic circuit connected to an input of a succeeding clocked logic circuit.
 41. A logic circuit as in claim 40, wherein said control logic circuit of each clocked logic circuit is a pass transistor control circuit, and during a first phase said precharge transistor of each clocked logic circuit is configured to precharge said output of said inverter to a low logic state, and during a second phase said clocking transistor of each clocked logic circuit is configured to activate said inverter such that the inverter output of approximately one of every two of said plurality of clocked logic circuits is not required to change states.
 42. A logic circuit as in claim 41, wherein said pass transistor control circuit for at least one of said plurality of clocked logic circuits comprises a pass transistor circuit.
 43. A logic circuit as in claim 41, wherein said pass transistor control circuit for at least one of said plurality of clocked logic circuits comprises a pair of complementary pass transistor circuits.
 44. A logic circuit as in claim 38, wherein said first and second clocking signals are complementary signals.
 45. A processor system, comprising: a processor; at least one memory device coupled to said processor, said at least one memory device including a logic circuit comprising: at least one control logic circuit; at least one inverter including a CMOS transistor pair having a gate of a first transistor coupled to a gate of a second transistor, said coupled gates being coupled to an output of said at least one control logic circuit, and a first source/drain region of said first transistor coupled to a first source/drain region of said second transistor, said coupled first source/drain regions being coupled to an output of said inverter, wherein a second source/drain region of said first transistor is coupled to a first potential terminal; at least one precharge transistor coupled to said inverter and configured to precharge said output of said inverter to a first logic state; and at least one clocking transistor coupled to said inverter and configured to selectively enable said output of said inverter.
 46. A processor system as in claim 45, wherein said first logic state is a low logic state.
 47. A processor system as in claim 45, wherein said at least one clocking transistor has a gate coupled to a first clocking signal and said at least one precharge transistor has a gate coupled to a second clocking signal.
 48. A processor system as in claim 47, wherein said first and second clocking signals are complementary signals.
 49. A processor system, comprising: a processor; at least one memory device coupled to said processor, said at least one memory device including a logic circuit comprising: at least one control logic circuit; at least one inverter including a CMOS transistor pair having a gate of a first transistor coupled to a gate of a second transistor, said coupled gates being coupled to an output of said at least one control logic circuit, and a first source/drain region of said first transistor coupled to a first source/drain region of said second transistor, said coupled first source/drain regions being coupled to an output of said inverter, wherein a second source/drain region of said first transistor is coupled to a first potential terminal; at least one clocking transistor having a gate coupled to a first clocking signal, a first source/drain region coupled to a second potential terminal, and a second source/drain region coupled to a second source/drain region of said second transistor; and at least one precharge transistor having a gate coupled to a second clocking signal, a first source/drain region coupled to said second potential terminal, and a second source/drain region coupled to said output of said inverter.
 50. A processor system as in claim 49, wherein during a first phase said precharge transistor is configured to precharge said output of said inverter to a low logic state, and during a second phase said clocking transistor is configured to activate said inverter such that said inverter output is not required to change states if said activated inverter first outputs said low state.
 51. A processor system as in claim 50, wherein during said first phase, said precharge transistor is configured to couple said output of said inverter to said second potential terminal.
 52. A processor system as in claim 50, wherein during said second phase, said clocking transistor is configured to couple said second source/drain region of said second transistor to said second potential terminal.
 53. A processor system as in claim 49, wherein said first clocking signal is initially in a low state and said second clocking signal is initially in a high state, permitting said precharge transistor to precharge said inverter output to a low state.
 54. A processor system as in claim 53, wherein when said first clocking signal transitions from said initial low state to a high state and said second clocking signal transitions from said initial high state to a low state, said inverter output is set according to said output of said control logic circuit.
 55. A processor system as in claim 50, wherein when said output of said control logic circuit initially attempts to place said inverter output in a low state, then said inverter output continues said low state of said precharge.
 56. A processor system as in claim 50, wherein when said output of said control logic circuit initially attempts to place said inverter output in a high state, then said inverter output transitions from said low state of said precharge to said high state.
 57. A processor system as in claim 49, wherein said at least one control logic circuit comprises a pass transistor control circuit.
 58. A processor system as in claim 57, wherein said pass transistor control circuit comprises a pass transistor circuit.
 59. A processor system as in claim 57, wherein said pass transistor control circuit comprises a pair of complementary pass transistor circuits.
 60. A processor system as in claim 49, wherein said second potential terminal is at ground potential.
 61. A processor system as in claim 49, wherein said clocking transistor is an NMOS transistor.
 62. A processor system as in claim 49, wherein said precharge transistor is an NMOS transistor.
 63. A processor system as in claim 49, wherein said first and second clocking signals are complementary signals.
 64. A processor system as in claim 49, wherein said at least one memory device is integrated on a same chip as said processor.
 65. A method of switching an output of a logic circuit, comprising: providing at least one control logic circuit having an output; providing at least one clocked inverter circuit having an input and an output, said input of said clocked inverter circuit being coupled to gates of first and second transistors of a CMOS transistor pair, and said output of said clocked inverter circuit being coupled to source/drain regions of said first and second transistors of said CMOS transistor pair; coupling another source/drain region of said first transistor to a first potential terminal; coupling said output of said control logic circuit to said input of said clocked inverter circuit; selectively activating said clocked inverter circuit according to a first clocking signal by coupling another source/drain region of said second transistor to a second potential terminal through a clocking transistor; and precharging said output of said clocked inverter circuit to a first logic state according to a second clocking signal by coupling said output of said clocked inverter circuit to a second potential terminal through a precharge transistor.
 66. A method as in claim 65, wherein said first logic state is a low logic state.
 67. A method as in claim 65, wherein during a first phase said precharge transistor is configured to precharge said output of said clocked inverter circuit to a low logic state, and during a second phase said clocking transistor is configured to activate said clocked inverter circuit such that said output of said clocked inverter circuit is not required to change states if said activated clocked inverter circuit first outputs said low logic state.
 68. A method as in claim 66, wherein during said first phase, said precharge transistor is configured to couple said output of said clocked inverter circuit to said second potential terminal.
 69. A method as in claim 66, wherein during said second phase, said clocking transistor is configured to couple said another source/drain region of said second transistor to said second potential terminal.
 70. A method as in claim 65, wherein said first clocking signal is initially in a low state and said second clocking signal is initially in a high state, permitting said precharge transistor to precharge said output of said clocked inverter circuit to a low state.
 71. A method as in claim 70, wherein when said first clocking signal transitions from said initial low state to a high state and said second clocking signal transitions from said initial high state to a low state, said output of said clocked inverter circuit is set according to said output of said control logic circuit.
 72. A method as in claim 70, wherein when said output of said control logic circuit initially attempts to place said output of said clocked inverter circuit in a low state, then said output of said clocked inverter circuit continues said low state of said precharge.
 73. A method as in claim 70, wherein when said output of said control logic circuit initially attempts to place said output of said clocked inverter circuit in a high state, then said output of said clocked inverter circuit transitions from said low state of said precharge to said high state.
 74. A method as in claim 65, wherein said at least one control logic circuit comprises a pass transistor control circuit.
 75. A method as in claim 74, wherein said pass transistor control circuit comprises a pass transistor circuit.
 76. A method as in claim 74, wherein said pass transistor control circuit comprises a pair of complementary pass transistor circuits.
 77. A method as in claim 65, wherein said second potential terminal is at ground potential.
 78. A method as in claim 65, wherein said first and second clocking signals are complementary signals. 